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simulating_verilog_the_right_way [2019/04/22 01:20]
yehowshua
simulating_verilog_the_right_way [2019/04/22 01:22] (current)
yehowshua [Example Use Case]
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 ==== Example Use Case ==== ==== Example Use Case ====
-Now here is something really neat! I can use verilator to compile the MAERI RTL into C++. I can then write C++ code that takes input which the MAERI DNN is to classify and converts it into a form MAERI can understand. I can then write yet more C code which controls MAERI'​s input ports in the correct way. I then wrap this code around the MAERI RTL which was converted into C++ code and can simulate MAERI on my computer. The exact C++ code I wrote to manage MAERI can be placed directly on the RISCV softcore and manage MAERI in hardware!!+Now here is something really neat! I can use verilator to compile the MAERI RTL into C++. I can then write C++ code that takes input which the MAERI DNN is to classify and converts it into a form MAERI can understand. I then write yet more C code which controls MAERI'​s input ports in the correct way. Finally, ​I wrap this code around the MAERI RTL/C++ and can simulate MAERI on my computer. The exact C code I wrote to manage MAERI can be placed directly on the RISCV softcore and manage MAERI in hardware!!
  
-Obviously the RISCV core has limitation. It is not so fast and only has the standardint.h library. I must write malloc and other basic system functions by hand. Thus there will be a few minor differences between the simulator C controller and the C controller I actually place on the FPGA. Also, the C controller must be simple/fast enough to fit in 3KB of memory - so it won’t have many levels of abstraction. But this definitely beats blindly writing an RTL controller for MAERI - and then having to debug it with a waveform viewer.+Obviously the RISCV core has limitation. It is not so fast and only has the standardint.h library. I must write malloc and other basic system functions by hand. Thus there will be a few minor differences between the simulator C controller ​code and the C controller ​code I actually place on the FPGA. Also, the C controller must be simple/fast enough to fit in 3KB of memory - so it won’t have many levels of abstraction. But this definitely beats blindly writing an RTL controller for MAERI - and then having to debug it with a waveform viewer.
  
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