Simulating verilog in an effective manner can be a challenging task. The verilog language provides a few structures for allowing the HDL designer to describe a small testbench effectively - but is rather inadequate for complex design. Such shortcomings become extremely painful in large complex design such as implementing and verifying a DNN in an FPGA. Fortunately, there is a solution. Open Source to the rescue once again!!

Verilator to the Rescue

Verilator allows you to compile your Verilog source into C++ code. Suddenly, anything that you can do with C++/C, you can do with your RTL. For example, if you have RTL that has video output, you can use verilator to display that video output within your windowing system via the X Windowing System for example.

I am currently building synthesizing the DNN accelerator MAERI for the ECP5 FPGA. To correctly serve inputs and manage memory, MAERI needs a controller. Instead of implementing the complex controller in Verilog, I use a software CPU on the FPGA. I can then compile C code for the core with gcc that manages memory and serves inputs. I have the host computer send pictures to the DNN for classification and load the results back from the DNN. Obviously, implementing the controller in Verilog would be a quite hefty and inflexible option.

Example Use Case

Now here is something really neat! I can use verilator to compile the MAERI RTL into C++. I can then write C++ code that takes input which the MAERI DNN is to classify and converts it into a form MAERI can understand. I then write yet more C code which controls MAERI's input ports in the correct way. Finally, I wrap this code around the MAERI RTL/C++ and can simulate MAERI on my computer. The exact C code I wrote to manage MAERI can be placed directly on the RISCV softcore and manage MAERI in hardware!!

Obviously the RISCV core has limitation. It is not so fast and only has the standardint.h library. I must write malloc and other basic system functions by hand. Thus there will be a few minor differences between the simulator C controller code and the C controller code I actually place on the FPGA. Also, the C controller must be simple/fast enough to fit in 3KB of memory - so it won’t have many levels of abstraction. But this definitely beats blindly writing an RTL controller for MAERI - and then having to debug it with a waveform viewer.


  • simulating_verilog_the_right_way.txt
  • Last modified: 2019/08/14 23:43
  • by yehowshua