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reading_data_and_address_with_a_logic_analyzer [2018/10/17 20:45]
michael
reading_data_and_address_with_a_logic_analyzer [2018/10/17 20:45] (current)
michael
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 I decided to take advantage of the processor direct slot by plugging in the Logic Analyzer at Digital Design Lab (DDL) directly into the [[Processor Direct Slot Macintosh SE | PDS]]. I decided to take advantage of the processor direct slot by plugging in the Logic Analyzer at Digital Design Lab (DDL) directly into the [[Processor Direct Slot Macintosh SE | PDS]].
  
-I first went to the DDL and wired up the Mac into the LA using this [[Processor Direct Slot Macintosh SE | pinout]]. I then ran the LA software using the PDS clock as the acquisition edge. {{:​mac_in_pds.jpg?​direct&​400|}}+I first went to the DDL and wired up the Mac into the LA using this [[Processor Direct Slot Macintosh SE | pinout]]. I then ran the LA software using the PDS clock as the acquisition edge.  
 + 
 +{{:​mac_in_pds.jpg?​direct&​400|}}
  
 Unfortunately,​ I didn't take a picture of data capture on the LA's screen. But the CPU cycled through approximately the same 200 addresses repeatedly with B2E3 constantly showing up on the data bus. I read through the Mac SE hardware documentation on startup procedures, and my best guess is that reset pin keeps getting pulled active. The reset vector resides at virtual address 0x0000 which is later translated by the BBU to different physical address '''''​update this'''''​. I stopped using the LA at DDL because of the difficulty and hassle. I built my own affordable LA described [[Purchasing an FPGA | here]]. Unfortunately,​ I didn't take a picture of data capture on the LA's screen. But the CPU cycled through approximately the same 200 addresses repeatedly with B2E3 constantly showing up on the data bus. I read through the Mac SE hardware documentation on startup procedures, and my best guess is that reset pin keeps getting pulled active. The reset vector resides at virtual address 0x0000 which is later translated by the BBU to different physical address '''''​update this'''''​. I stopped using the LA at DDL because of the difficulty and hassle. I built my own affordable LA described [[Purchasing an FPGA | here]].
  • reading_data_and_address_with_a_logic_analyzer.txt
  • Last modified: 2018/10/17 20:45
  • by michael