Towards Simulating Verilog With Haskell

Often times when simulating digital circuits, you wonder why a signal changed during a certain cycle. You can trace your way back through the RTL sources and slowly begin to figure out why. For larger designs however, this process is often cumbersome. So I've decided to work on an RTL simulator that can form hypotheses about why a certain signal changed in a given cycle.

The first step to this is being able to parse digital circuits into an AST. For this, I've used Yosys to convert Verilog into RTLIL. From there, I've written a Haskell frontend that parses RTLIL. I think the next step is to define the semantics of exactly what it means to evaluate RTLIL in pure Haskell. Then I'll likely need to define computational primitives from which I can construct a schedulable computaion graph. I'd also need to build out a backend that lowers to something much faster than Haskell such as lowering to C or even lowering to target Tenstorrent's Wormhole compute cards which seem(by way of micro-architecture) incredibly well suited to rapidly evaluating graphs including digital circuit graphs. I'll probably also need an SMT solver for forming hypotheses for observed signal changes in the saved simulation output. So many things to do... But for now, one step at a time.

You can find the code I've written so far here.

The tool is called Haskellator.