A New RTL Called Polished
As aforementioned, I’m creating a new RTL called Polished.
It’s called Polished because it will provide a polished digital logic design experience from start to finish. Polished will emit verilog, but through RTLIL+Yosys, Polished should be able to skip Verilog entirely and emit gate-level netlists, good for place-and-routing.
Polished RTL is part of a larger ecosystem that includes:
- Polished - the RTL
- Wax - auxiliary libraries for the Polished RTL including things such as Asynchronous Fifos, pipelined multipliers, floating point units, AXI buses, caches, and mesh networks.
- Finish - larger auxiliary components to make a design useful in the real world such as PCIe controllers, Ram controllers, USB controllers, etc.
- Polished Expo - a modern waveform viewer
- TBD - Some tools for inexpensive synthesis and place and routing to a virtual technology node. This is primarily to allow the designer to get a cost estimate on how the fmax and area of the design.
Higher Level View
I’ve been working on the guts of Polished that will go into the simulation engine backend. These guts are called BitVectors, which is a library written in Nim.
After some thought, it turns out that the BitVectors library is re-usable across multiple components of the Polished ecosystem.
Below is a high level diagram showing my current current mental model of how different components of the ecosystem might fit together. I haven’t yet given extensive thought to how Wax and Finish would fit in, so they’re not included in the diagram.
Also, nimulatorPPC is a distinct project from Polished, but it is included since as of the time of this writing, I’m building the BitVectors library to also target VCDWriter which is to be used in nimulatorPPC.
I’ve also been reflecting on the look and feel of Polished. This is what I’ve got so far:
type state = enum start, middle, end var mybus = Io: Input data = Signed(31..0) Input address = Signed(31..0) Output valid = Signed(31..0) var myMod = Module: var io = Io: Input count = Signed(7..0) Output b = Unsigned(7..0) Output c = Signed(1024.Max) Input hash = Signed(127..0, reset=9876546787654348765'bi) Input mystate = state.PolishedEnum() InOut bus = mybus() io.count.sync := io.count + 1 io.b := 3 # the following will fail because we # already assigned to the count's sync domain # count.comb := b