I firmly believe that designing custom silicon is currently needlessly difficult. I’m also an unabashed supporter of auditable, privacy-respecting silicon.

Lastly, I’m just another programmer with a fancy camera working for a startup. The date on a page is when it was first written, not when it was last edited. Find my archived content here

For quick reference, here is the yosys manual as of July 26, 2021.

A New RTL Called Polished


As aforementioned, I’m creating a new RTL called Polished. It’s called Polished because it will provide a polished digital logic design experience from start to finish. Polished will emit verilog, but through RTLIL+Yosys, Polished should be able to skip Verilog entirely and emit gate-level netlists, good for place-and-routing. Polished RTL is part of a larger ecosystem that includes: Polished - the RTL PolishedVM - Hardware simulation backend. Wax - auxiliary libraries for the Polished RTL including things such as Asynchronous Fifos, pipelined multipliers, floating point units, AXI buses, caches, and mesh networks.…
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Multiplying Large Numbers


Recently, I mentioned that I’m working on a new RTL called Polished. Polished will have a built in simulator backend that aims to be very fast. Since wires in a netlist can have any length, the backend must be able to handle any arithmetic operation between two wires. The final implementation that will end up going into Polished will be different from the toy example present below in the following ways:…
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On The State of Digital Logic Design


Imagine if everytime you wanted to deploy the most basic of websites you had to: hire a computer building expert to build a custom PC hire an expert in networking to get your PC online hire an expert in installing Linux onto the PC hire an expert in install Python hire an expert in installing Flask hire an expert in writing integrating flask, with your HTML templates with your javascript client side scripts That would be utter insanity.…
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BigInt in nimVM vs Python


I’m currently working on a digital logic DSL in Nim that is called Polished, because it provides a polish digital logic design experience. I need to decide whether or not to do compile-time or runtime elaboration of the DSL as compile-time execution in Nim run’s on the nimVM. The nimVM is known for being on the slow side; I wanted to know just how slow, so I decided to do some testing with BigInt in both nimVM and Python, but first some background:…
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