# why migen

## Introduction¶

Migen is a high level hardware description language(not to be confused with HLS - high level synthesis language). Much like Chisel and SpinalHDL, Migen allows the hardware designer to use modern language features such as OOP to describe hardware. Instantiating a bus between two devices in hardware can be as simple as passign the device to an instantiation of the bus class. Whereas Chisel and Spinal are both written in Scala, Migen is written in Python3.

• Migen+LiteX = builtin support for common Xilinx FPGAs as well as the FOSS toolchains such as yosys+nextpnr for Lattice FPGAs. Instantiating Ethernet on the ECP5 FPGA can be a simple as importing LiteX and migen and then calling build() which will generate the bitstream for the repsective ECP5.