Towards Simulating Verilog With Haskell
Earlier this year, I thought it would be a good idea to simulate RTL in Haskell...
Read more ⟶
Thoughts Probably Occur Outside Time and Space
From the Pythagorean Theorem to the Existence of a Soul: A Journey of Faith and Reason
Read more ⟶
Sunsetting the Fastwave Backend
What I Learned
Read more ⟶
Unpacking Challenges from the POWER ISA: Why I'm Exploring RISC-V's Formal Models
Exploring the complexities of the POWER ISA led me to consider formal models as a more intuitive alternative to traditional prose-based specifications.
Read more ⟶
AI as a Utility
AI is now part of my utility bill.
Read more ⟶
Improving The Bluespec Compiler
Some notes that should help with adding features to the Bluespec Compiler
Read more ⟶
An Interesting SBIR Topic
SBIR related to seL4 and Custom Hardware
Read more ⟶
Current Interests / Top Of Mind
Language Eagerness; Concurrency Safety Primitives; Differentiable Programming
Read more ⟶
GoodBye Rust?
It might be time to leave Rust for Good?
Read more ⟶
Taking a look at Clash HDL
I've hit some practical issues with Bluespec, prompting me to take another look at Clash
Read more ⟶