Towards Simulating Verilog With Haskell


Earlier this year, I thought it would be a good idea to simulate RTL in Haskell...
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Thoughts Probably Occur Outside Time and Space


From the Pythagorean Theorem to the Existence of a Soul: A Journey of Faith and Reason
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Sunsetting the Fastwave Backend


What I Learned
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Unpacking Challenges from the POWER ISA: Why I'm Exploring RISC-V's Formal Models


Exploring the complexities of the POWER ISA led me to consider formal models as a more intuitive alternative to traditional prose-based specifications.
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AI as a Utility


AI is now part of my utility bill.
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Improving The Bluespec Compiler


Some notes that should help with adding features to the Bluespec Compiler
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An Interesting SBIR Topic


SBIR related to seL4 and Custom Hardware
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Current Interests / Top Of Mind


Language Eagerness; Concurrency Safety Primitives; Differentiable Programming
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GoodBye Rust?


It might be time to leave Rust for Good?
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Taking a look at Clash HDL


I've hit some practical issues with Bluespec, prompting me to take another look at Clash
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